1 Technical Field of the Invention
The present invention relates generally to an improvement on an information processing apparatus such as a microcomputer which has a CPU and an auxiliary arithmetic unit such as a coprocessor for achieving high-speed operations.
2 Background Art
Computer systems are known in the art which perform a pipelined operation in which a plurality of instructions are executed in a plurality of parallel steps concurrently and in an overlapped fashion. Specifically, a CPU divides the process of executing each instruction into five stages: IF (instruction fetch), ID (instruction decode), EX (execution), MA (memory access), and WB (write back). The IF stage is a fetch operation which reads an instruction out of a peripheral memory such as a ROM or a RAM. The ID stage is a decode operation in which the instruction is decoded to indicate an operation to be carried out. The EX stage is an execution operation in which the decoded operation is carried out. The MA stage involves a memory access to the peripheral memory for transmission of data between the memory and the CPU. The WB stage is a writing operation to write data in the peripheral memory.
In recent years, microcomputers used in machine control are required to achieve a high-speed operation of the CPU and improvement of ability to process digital signals.
While the high-speed operation of the CPU may be realized to some extent by the pipelined operation as described above, the improvement of ability to process digital signals requires either of the following two methods.
The first is to install a DSP (Digital Signal Processor) in the microcomputer independent of the CPU.
The second is to connect a coprocessor designed to perform special arithmetic operations such as calculation of logarithm or the sum of products which the CPU cannot execute at high speeds with the CPU using a bus for allowing the coprocessor to perform the special arithmetic operations in response to a command issued by the CPU.
The former is not practical because the DSP is bulky, and it is difficult to reduce the size of an LSI.
The latter encounters a difficulty in executing operations concurrently in the CPU and the coprocessor. Specifically, even if the CPU and the coprocessor gain access to different memories during operations, data from the CPU and the coprocessor are transmitted through the same bus, thus resulting in difficulty in proper access to the memories. The latter is, thus, useful in speeding the operation of the CPU, but has a limitation of improvement of ability to process digital signals.